With the SCTL, all functions inside the loop must execute within a single tick. An explanation of the enable chain is beyond the scope of this document, but is used to ensure dataflow when the FPGA VI is compiled into a bitfile.Īdditionally, each function inside the While Loop will require at least one tick to execute, although functions will execute in parallel if there is no data dependency.
This is because of the enable chain used in the compiled FPGA VI. Using a traditional While Loop in your FPGA VI takes an absolute minimum of 3 ticks to execute each iteration. How much faster will programs execute using the SCTL? You cannot dynamically change the timing properties of the Timed Loop when used with an FPGA target. You can use the SCTL with derived clocks to clock the loop at a rate other than 40 MHz. The default selection is the 40 MHz FPGA global clock. When used with an FPGA target this loop executes all functions inside within one tick of the FPGA clock you have selected. Timed Loop structures are always SCTLs when used in an FPGA VI. The single-cycle Timed Loop (SCTL) is a special use of the LabVIEW Timed Loop structure.
Solution What is the single-cycle Timed Loop?